library ieee;
use ieee.std_logic_1164.all;

entity comperator is
	generic (
		size				: positive
	);
	port(
		signed			: in  std_logic;
		opcode			: in  std_logic_vector(3 downto 0);
		op1					: in  std_logic_vector(size-1 downto 0);
		op2					: in  std_logic_vector(size-1 downto 0);

		result			: out std_logic
	);
end entity;

architecture behaviour of comperator is
	signal signed_greater				: std_logic;
	signal unsigned_greater			: std_logic;

	signal equal								: std_logic;
	signal greater							: std_logic;
	signal lesser								: std_logic;
begin
	l_signed: entity work.signed_comperator(behaviour)
		generic map (
			size => size
		)
		port map (
			op1 => op1,
			op2 => op2,
			greater => signed_greater
		);

	l_unsigned: entity work.unsigned_comperator(behaviour)
		generic map (
			size => size
		)
		port map (
			op1 => op1,
			op2 => op2,
			greater => unsigned_greater
		);

	greater <= signed_greater when signed = '1' else
					unsigned_greater;
	lesser <= not (greater or equal);

	result <= (opcode(3) and not equal) or 
					(opcode(2) and lesser) or
					(opcode(1) and greater) or
					(opcode(0) and equal);

	process(op1,op2) begin
		if (op1 = op2) then
			equal <= '1';
		else
			equal <= '0';
		end if;
	end process;
end architecture;